The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a monitor circuit for detecting a characteristic of an internal circuit.
In a semiconductor integrated circuit using a CMOS logic gate, as a method for reducing electric power, DVFS (Dynamic Voltage and Frequency Scaling) for controlling a power source voltage depending on a required speed is effective.
Representatives of a method for controlling a power source voltage include a method based on a delay monitor. Since there are characteristic variations in a chip, performance obtained by subtracting a certain degree of margin from chip performance detected with the delay monitor is lowest performance in a real chip. The voltage needs to be controlled such that the lowest performance satisfies the required speed. Here, when the accuracy of the chip performance detected by the delay monitor is low, it is necessary to overestimate the margin, and consequently the power source voltage is controlled to be high, resulting in increased power consumption. Accordingly, by, e.g., disposing multiple monitors in the chip, and retrieving a result from the monitor operating at a lowest speed, the margin to be estimated can be reduced.
FIG. 1 is a block diagram schematically showing a configuration of a semiconductor integrated circuit device according to a prior art technology. The semiconductor integrated circuit device of FIG. 1 includes a power supply circuit and a chip. Here, the chip includes multiple monitor circuits, a detection circuit, and a control circuit. The multiple monitor circuits detect a characteristic of the chip at mutually different positions, and output the results of detection toward the detection circuit. The detection circuit outputs an overall result obtained by combining the multiple detection results transmitted from the multiple monitor circuits toward the control circuit. The control circuit generates a control signal in accordance with the overall result. The power supply circuit adjusts a power source voltage VDD in accordance with the control signal, and supplies the adjusted power source voltage VDD to the chip.
In the semiconductor integrated circuit device of FIG. 1, when the characteristic variations in the chip are of a known magnitude, the average value of the detection results from the multiple monitors is calculated, and the variations are subtracted therefrom to allow the lowest performance in the chip to be estimated.
With regard to the foregoing, Japanese Unexamined Patent Publication No. 2009-10344 discloses a description related to a semiconductor integrated circuit. The semiconductor integrated circuit includes a power source voltage supply means for supplying a power source voltage to one or more internal circuits. The semiconductor integrated circuit has the following characteristic feature. That is, the circuit includes multiple process monitor means disposed at multiple locations over the circuit to operate in accordance with the power source voltage, and detect monitor data on the individual locations. The power source voltage supply means generates power source voltages in accordance with the multiple monitor data items mentioned above, and supplies the power source voltages to the internal circuits.